College of Information and Communication Engineering Sungkyunkwan University, Korea;
College of Information and Communication Engineering Sungkyunkwan University, Korea;
College of Information and Communication Engineering Sungkyunkwan University, Korea;
College of Information and Communication Engineering Sungkyunkwan University, Korea;
Clocks; Delay lines; Delays; Jitter; Power demand; Time-frequency analysis; Phase locked loops;
机译:使用多条压控延迟线的双回路延迟锁定回路
机译:使用脉宽比较器和双注入技术的2.4GHz 1.5mW数字乘法延迟锁定环路
机译:2a ?? 4 GHz快速锁定倍频延迟锁定环
机译:8.9 MW,0.6-2 GHz快速锁定延迟锁定环,使用双延迟线具有相位搅拌机
机译:用于多个时钟相位/延迟生成的延迟锁定环路。
机译:具有可调范围CMOS延迟锁定环路的亚皮秒抖动设计适用于高速和低功耗应用
机译:A 2-4 GHz快速锁定频率倍增延迟锁定环