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Serial to parallel conversion by extracting even and odd numbered data pulses synchronously with leading and trailing edges of clock pulses respectively

机译:通过分别与时钟脉冲的上升沿和下降沿同步提取偶数和奇数数据脉冲来进行串行到并行转换

摘要

A data transfer method allows improved data transfer speed without increasing the number of signal lines. After dividing data to be transferred into odd-numbered data and even-numbered data, the odd-numbered data are sequentially read at timing of a leading edge of each clock pulse and the even-numbered data are sequentially read at timing of a trailing edge of each clock pulse. Thereafter, a data transfer completion indicator is appended to one of the odd-numbered and even-numbered data strings. A transfer clock signal includes a fixed level pulse in a period of time corresponding to the data transfer completion indicator. The one of the odd-numbered and even-numbered data strings followed by the data transfer completion indicator, the other of the odd-numbered and even-numbered data strings, and the transfer clock signal are transferred through different signal lines.
机译:数据传输方法可以提高数据传输速度,而无需增加信号线的数量。在将要传送的数据划分为奇数数据和偶数数据之后,在每个时钟脉冲的上升沿的定时顺序读取奇数数据,并且在下降沿的定时顺序读取偶数数据。每个时钟脉冲。此后,将数据传输完成指示符附加到奇数和偶数数据串之一。传输时钟信号在与数据传输完成指示符相对应的时间段内包括固定电平的脉冲。奇数和偶数数据串中的一个紧跟着数据传输完成指示符,奇数和偶数数据串中的另一个,以及传输时钟信号通过不同的信号线传输。

著录项

  • 公开/公告号GB2365723A

    专利类型

  • 公开/公告日2002-02-20

    原文格式PDF

  • 申请/专利权人 * NEC CORPORATION;

    申请/专利号GB20010004437

  • 发明设计人 TAKESHI * ANZAI;

    申请日2001-02-22

  • 分类号G11C7/00;G06F13/38;

  • 国家 GB

  • 入库时间 2022-08-22 00:23:17

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