Edge-controlled asynchronous logic circuit with buffer storage - has two holding stages clocked by leading and trailing edges of output pulses from logic section also providing ready signal

摘要

The results of combination of signals obtd. from the rising and the falling edges of a request input (REQI) are buffer-stored in respective holding stages (L1,L2) for selective output (O) via a multiplexer (DMUX) addressed by signals to a readiness input (RDYI) and from a so-called Mueller-C element (MC). The Muller-C inputs are supplied from the readiness output (RDY) of the edge-controlled asynchronous logic section (FAL) and from a reception confirmation input (ACKI). The demultiplexer consists of two 3-input AND gates (A1,A2) with parallel outputs. ADVANTAGE - Very simple modular circuit can be combined with, or built up into, many types of asynchronous logic.