Buffer circuit for receiving logic signal, in particular clock signal, comprising means for inhibition of transfer in selected time intervals related to pulse leading and trailing edges

摘要

The buffer circuit comprises the transfer means including a switch (SW1) and two inverter gates (11,12) connected in series, the inhibition block (IB) for inhibiting the transfer means during all or part of the pulse rise and decay times, that is in the intervals (t1-t2) and (t3-t4), and the storage means including a switch (SW2) and two inverter gates (13,14) for maintaining the output at a logic value which was present during the periods of inhibition. The switch (SW1) is controlled by the inhibition signal (INHIB) delivered by the inhibition block (IB). The inhibition block contains two asymmetric inverter gates (15,16) with low and high threshold voltages (VtI,Vth), and an exclusive-OR or NOT exclusive-OR (NXOR) gate receiving the signals (Sa,Sb) delivered by the asymmetric inverter gates. The inverter gates (11,13) form a memory cell, and the switch (SW2) is controlled by the inverse inhibition signal (/INHIB). An integrated circuit such as serial input/output memory store receives a clock signal by the intermediary of the buffer circuit.