The leading edge and the trailing edge of the clock pulse being both, the device null which converts D die flip-flop to the B die flip-flop which the sample it is possible the data

摘要

PURPOSE: To automatically suite a delay element to the timing request of a flip flop by obtaining the first input of an exclusive OR circuit as the clock input of a B-type flip flop, connecting the second input with the D input of a first D-type flip flop, and short-circuiting this D input with the QN output of the same first D-type flip flop. CONSTITUTION: A flip flop 4 operates switching in each clock transfer, this operates as a divider by a divisor 2, the inversion of a clock input 2d of a flip flop 2 is applied, and preliminary arrangement for the next transfer is applied. Propagation delay is normally equal to the minimum pulse width or larger than that, and the minimum clock width of the last one for the both flip flops depends on the propagation time of the flip flop 2 to which the delay time by the exclusive OR circuit 3 should be added. When the delay time of the exclusive OR circuit 3 is ignored, the smaller delay time is made correspond to the propagation time of a flip flop 4.