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MICROCOMPUTER, BUS CONTROL CIRCUIT, AND DATA ACCESS METHOD FOR MICROCOMPUTER

机译:微计算机,总线控制电路和微计算机的数据访问方法

摘要

PROBLEM TO BE SOLVED: To efficiently access a plurality of devices differed in access speed by use of a common bus.;SOLUTION: When a second access request to a second device 4 is generated from a CPU 2 during an access processing according to a first access request to a first device 3, an access completion time determination part 5a determines the antedate-postdate relation between the completion time of the access processing to the first device 3 and the earliest time of the access processing to the second device 4 can be completed. When it is determined that the access processing to the second device 4 can be completed earlier than the completion time of the access processing to the second device 4, the access to the second device 4 according to the second access request is executed by a bus access part 5b during the access processing cycle according to the first access request to the first device 3.;COPYRIGHT: (C)2003,JPO
机译:解决的问题:通过使用公共总线有效地访问访问速度不同的多个设备。解决方案:当在根据第一优先级的访问处理期间从CPU 2生成对第二设备4的第二访问请求时对第一设备3的访问请求,访问完成时间确定部5a确定对第一设备3的访问处理的完成时间与对第二设备4的最早访问处理的时间之间的先行日期关系。 。当确定可以比对第二设备4的访问处理的完成时间更早地完成对第二设备4的访问处理时,通过总线访问来执行根据第二访问请求的对第二设备4的访问。部分5b根据对第一设备3的第一访问请求在访问处理周期中;版权:(C)2003,JPO

著录项

  • 公开/公告号JP2003271551A

    专利类型

  • 公开/公告日2003-09-26

    原文格式PDF

  • 申请/专利权人 FUJITSU LTD;

    申请/专利号JP20020073919

  • 发明设计人 AKASAKA NOBUHIKO;

    申请日2002-03-18

  • 分类号G06F13/42;G06F12/06;G06F13/16;G06F13/36;G06F15/78;

  • 国家 JP

  • 入库时间 2022-08-22 00:18:49

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