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CARRY OUTPUT CIRCUIT FOR BINARY NUMBER ADDITION AND BINARY NUMBER ADDITION CIRCUIT

机译:进行二进制数加法和二进制数加法电路的输出电路

摘要

PROBLEM TO BE SOLVED: To provide a carry output circuit suppressing delay time without complicating the circuit even when the number of input digits increases. ;SOLUTION: The carry output circuit is provided with a low-order digit carry part 151 computing the low-order digit values of respective numerical values A and B and outputting low-order carry signals, a pertinent digit all 1 detection part 152 detecting that the respective OR output values of the pertinent addition digits of the respective numerical values A and B are all 1, a pertinent digit AND output part 44a outputting a first temporary pertinent carry signal to the arithmetic part of highorder digits when input is present from both of the low-order digit carry part 151 and the pertinent digit all 1 detection part 152, a pertinent digit carry part 153 computing the respective values of the pertinent addition digits of the respective numerical values A and B and outputting a second temporary pertinent carry signal to the arithmetic part of the high-order digits and a pertinent digit OR output part 44b outputting pertinent carry signals to the arithmetic part of the high-order digits when at least one of the first temporary pertinent carry signal from the pertinent digit AND output part 44a and the second temporary pertinent carry signal from the pertinent digit carry part 153 is inputted.;COPYRIGHT: (C)2003,JPO
机译:解决的问题:提供一种即使在输入位数增加的情况下也能抑制延迟时间而不使电路复杂化的进位输出电路。 ;解决方案:进位输出电路配备有低位数字进位部分151,用于计算各个数值A和B的低位数字值并输出低位进位信号,相关数字全1检测部分152检测到各个数值A和B的相关加法数字的各个OR输出值均为1,相关数字AND输出部分44a在两个输入都存在时向高阶数字的算术部分输出第一临时相关进位信号。低位数字进位部分151和相关数字全1检测部分152,相关数字进位部分153计算各个数值A和B的相关相加数字的各自值,并输出第二临时相关进位信号到高位数字的算术部分和相关数字或输出部分44b,将相关的进位信号输出到高阶数字的算术部分当输入来自相关数字AND输出部分44a的第一临时相关进位信号和来自相关数字进位部分153的第二临时相关进位信号中的至少一个时; COPYRIGHT:(C)2003,JPO

著录项

  • 公开/公告号JP2003044268A

    专利类型

  • 公开/公告日2003-02-14

    原文格式PDF

  • 申请/专利权人 INTERNATL BUSINESS MACH CORP IBM;

    申请/专利号JP20010213054

  • 发明设计人 TANAKA NOBUYASU;

    申请日2001-07-13

  • 分类号G06F7/50;

  • 国家 JP

  • 入库时间 2022-08-22 00:17:42

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