首页> 外国专利> INTEGRATED DRAM MEMORY CIRCUIT, ROW ADDRESS CIRCUIT, ROW CONTROL CIRCUIT, AND METHOD FOR REFRESHING ROW CONTROL CIRCUIT AND DRAM MEMORY AND GENERATING ROW ADDRESS

INTEGRATED DRAM MEMORY CIRCUIT, ROW ADDRESS CIRCUIT, ROW CONTROL CIRCUIT, AND METHOD FOR REFRESHING ROW CONTROL CIRCUIT AND DRAM MEMORY AND GENERATING ROW ADDRESS

机译:集成的DRAM存储器电路,行地址电路,行控制电路以及刷新行控制电路和DRAM存储器并产生行地址的方法

摘要

PROBLEM TO BE SOLVED: To overcome such defect that 'enable' of a row selection circuit is delayed until an appropriate address source is decided in a circuit and a method for an integrated circuit memory.;SOLUTION: In a circuit and a method for an integrated circuit memory, a look-ahead function giving a refresh command to a device is incorporated at least one cycle before actual internal refresh operation occurs. An active cycle is performed with the same clock as application of an outer command. An active command is not changed, is performed with the same clock cycle as generation of the active command. The active command can be performed directly without waiting for decision whether a row address latch is to be supplied at outside or inside.;COPYRIGHT: (C)2003,JPO
机译:解决的问题:为了克服这样的缺陷,行选择电路的“使能”被延迟,直到在电路和用于集成电路存储器的方法中确定适当的地址源为止;解决方案:在电路和用于存储器的方法中在集成电路存储器中,在发生实际的内部刷新操作之前,至少要包含一个周期以向设备提供刷新命令的超前功能。激活周期的执行与外部命令的应用时钟相同。活动命令不会更改,它以与活动命令生成相同的时钟周期执行。可以直接执行激活命令,而无需等待决定是在外部还是在内部提供行地址锁存器。;版权所有:(C)2003,JPO

著录项

  • 公开/公告号JP2003242777A

    专利类型

  • 公开/公告日2003-08-29

    原文格式PDF

  • 申请/专利权人 UNITED MEMORIES INC;SONY CORP;

    申请/专利号JP20020247223

  • 发明设计人 JONES JR OSCAR FREDERICK;KIM C HARDY;

    申请日2002-08-27

  • 分类号G11C11/406;G11C11/408;

  • 国家 JP

  • 入库时间 2022-08-22 00:17:19

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