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ETCH STOP LAYER FOR SILICON (SI) VIA ETCH IN THREE-DIMENSIONAL (3-D) WAFER-TO-WAFER VERTICAL STACK
ETCH STOP LAYER FOR SILICON (SI) VIA ETCH IN THREE-DIMENSIONAL (3-D) WAFER-TO-WAFER VERTICAL STACK
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机译:硅片(SI)的蚀刻停止层,通过三维(3-D)晶圆对晶圆垂直堆栈进行蚀刻
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摘要
A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
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