首页> 外国专利> Arrangement for back-biasing multiple integrated circuit substrates at maximum supply voltage among all circuits

Arrangement for back-biasing multiple integrated circuit substrates at maximum supply voltage among all circuits

机译:在所有电路中以最大电源电压对多个集成电路衬底进行背偏置的装置

摘要

A diode coupling-based arrangement back-biases each of the semiconductor substrates of a plurality of integrated circuits at the maximum (e.g., most negative) DC voltage applied to any individual circuit, irrespective of a potential variation in applied DC voltages. Each semiconductor chip/substrate includes an auxiliary terminal to which each DC voltage terminal for that chip is diode-coupled. The auxiliary voltage terminal is connected to the underside biasing and thermal dissipation pad of the substrate. When multiple packages are mounted and conductively joined to a shared metallic dissipation region of a support substrate, all auxiliary voltage terminals will be connected in common, so as to back-bias each semiconductor substrate to the most maximum (e.g., most negative) of all applied DC voltages.
机译:基于二极管耦合的布置以施加到任何单个电路的最大(例如,最负的)DC电压向多个集成电路的每个半导体衬底反向偏置,而不管施加的DC电压的电势变化如何。每个半导体芯片/基板包括辅助端子,用于该芯片的每个DC电压端子被二极管耦合到该辅助端子。辅助电压端子连接到基板的下侧偏置和散热垫。当安装多个封装并将其导电连接到支撑基板的共享金属耗散区时,所有辅助电压端子将被公共连接,从而将每个半导体基板反向偏置到所有半导体基板的最大(例如,最大负值)施加的直流电压。

著录项

  • 公开/公告号US2003183922A1

    专利类型

  • 公开/公告日2003-10-02

    原文格式PDF

  • 申请/专利权人 INTERSIL AMERICAS INC.;

    申请/专利号US20020114142

  • 发明设计人 LEONEL E. ENRIQUEZ;DOUGLAS L. YOUNGBLOOD;

    申请日2002-04-02

  • 分类号H01L23/10;H01L21/48;

  • 国家 US

  • 入库时间 2022-08-22 00:09:39

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