A buffer is provided that has a high access time and operates with reduced power consumption. The buffer includes n write word line registers (400), each of which an output is directly connected to a word line driver. Thus, a word line is driven to access a memory cell array. All the word line registers are cascaded in a ring form. The write START signal 41 acting as a synchronous set input is input to the write word line register (400) corresponding to the least significant address. The write strobe (STB) signal 42 is input to the write word line registers connected in a ring form. When the write strobe signal 42 is active, the write word line registers operate like a shift register. When the write strobe signal 42 is not active, all the write word line registers hold a current value.
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