Memory-write decision circuit capable of simultaneously processing multiple items of data, and ATM switch having said circuit

摘要

Disclosed is device for suppressing a rise in the operating speed of the buffer controller in an ATM switch and reducing the operating speed in the write decision section of the switch. In a memory-write control circuit, data to be written to a memory having a predetermined memory capacity is provided with a priority. The circuit renders a write-enable/disable decision in such a manner that data of low priority will not be written to the memory in excess of a threshold value and data of high priority will not be written to the memory in excess of the memory capacity. A write decision circuit compares the threshold value and present queue length if the input data is valid data and, moreover, the data has a low priority, and compares the maximum capacity of the memory and the present queue length if the input data is valid data and, moreover, the data has a high priority, thereby to render an enable/disable decision with regard to writing of the input data to the memory. The write decision circuit converts multiple items of serially input control information to parallel data and renders the memory write-enable/disable decision with regard to multiple items of control information that have been rendered parallel.