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Has the memory writing judgment circuit and the said circuit of multiple data simultaneous processing the ATM switch

机译:具有存储器写入判断电路和多个数据所述电路同时处理ATM开关

摘要

PROBLEM TO BE SOLVED: To provide a device that suppresses increase in an operating speed of a buffer control section of an ATM switch and especially reduces an operating speed in a write discrimination section.;SOLUTION: In a memory write control circuit where priority is placed onto data written in a memory with a prescribed memory capacity, data with lower priority are not written in memory in excess of a threshold value, and data with higher priority are not written in the memory in excess of the memory capacity through discrimination of write propriety, the write discrimination circuit that compares the threshold value with a current queue length when input data are valid data with lower priority or compares the maximum capacity of the memory with the current queue length when the input data are data with higher priority so as to discriminate the propriety of data write to the memory, converts control information sets received serially into paralleled data and discriminates the write propriety of the control parallel information sets to the memory at the same time.;COPYRIGHT: (C)2002,JPO
机译:解决的问题:提供一种抑制ATM交换机的缓冲器控制部分的操作速度的增加,特别是降低写识别部分的操作速度的装置。解决方案:在具有优先权的存储器写控制电路中将具有指定存储容量的存储器中的数据写入具有预定阈值的存储器中的数据,通过区分写入适当性,将优先级较低的数据不超过阈值写入存储器,并且将优先级较高的数据不超过存储器容量写入存储器,写鉴别电路,当输入数据是具有较低优先级的有效数据时,将阈值与当前队列长度进行比较;或者,当输入数据是具有较高优先级的数据时,将存储器的最大容量与当前队列长度进行比较,以进行区分将数据写入存储器的适当性,将串行接收的控制信息集转换为并行数据,并区分wri同时将控制并行信息集存储到内存中。版权所有:(C)2002,JPO

著录项

  • 公开/公告号JP3533164B2

    专利类型

  • 公开/公告日2004-05-31

    原文格式PDF

  • 申请/专利权人 日本電気通信システム株式会社;

    申请/专利号JP20000282606

  • 发明设计人 嶋田 耕臣;

    申请日2000-09-18

  • 分类号H04L12/56;

  • 国家 JP

  • 入库时间 2022-08-21 23:24:43

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