Wakeup circuit for computer system that enables codec controller to generate system interrupt in response to detection of a wake event by a codec

摘要

A wake up circuit for a computer system with a codec controller. The circuit provides a wakeup signal to the computer system when a codec detects an event that requires the system to become active. This signal is provided whether the communications link between the codecs and their controller is active or inactive. When the link is inactive, as indicated by the absence of a bit clock, a data signal on any of the codec input lines triggers the controller to send a power activation signal to the system and to initiate an activation of the codec link. If the link is already active, the general purpose input status change bit is transmitted to the controller, which writes it into a register that is used to trigger a power activation signal to the system. An enable input permits the wakeup signal to be enabled or disabled under program control. The wakeup signal can be used to trigger a system management interrupt or other interrupt suitable for initiating a system resume function.