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Method and apparatus for estimating elmore delays within circuit designs
Method and apparatus for estimating elmore delays within circuit designs
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机译:估计电路设计中的埃尔莫尔延迟的方法和装置
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摘要
A system for rapidly accurate Elmore delays is disclosed which uses circuit simulations with different circuit configurations to generate Elmore delay models. From data generated by the simulations, Elmore delays are represented as functions of a capacitance charge and device width for a variety of device configurations. Similarly, accurate capacitance models are determined for each device. To determine an Elmore delay for a discharge path, the appropriate models are applied to each device and summed together. Within a timing verifier, the present invention can rapidly determine critical paths which require additional consideration.
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