Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism

摘要

A method and computer readable storage medium for estimating total path delay in an integrated circuit design include of receiving as input a number of stage delays and stage delay variations constituting a path in an integrated circuit design. A sum of the stage delays, a worst case sum of the stage delay variations, and a root-sum-square of the stage delay variations are calculated. A a value of a weighting function is calculated as a function of the number of stage delays. A a weighted sum of the worst case sum of the stage delay variations and the root-sum-square of the stage delay variations is calculated from the weighting function. The weighted sum is generated as output to estimate total path delay.