Method of estimating a total path delay in an integrated circuit design with stochastically weighted conservatism

摘要

A method and computer program product for estimating total path delay in an integrated circuit design includes steps of: (a) receiving as input a number of stage delays and stage delay variations constituting a path in an integrated circuit design; (b) calculating a sum of the stage delays; (c) calculating a worst case sum of the stage delay variations; (d) calculating a root-sum-square of the stage delay variations; (e) calculating a value of a weighting function; (f) calculating a weighted sum of the worst case sum of the stage delay variations and the root-sum-square of the stage delay variations from the weighting function; and (g) generating as output the weighted sum as a total path delay.