Method and computer program for estimating speed-up and slow-down net delays for an integrated circuit design

摘要

A method and computer program product that provide a savings in run time for calculating net delays with cross-talk include steps of providing a coupling capacitance, a net capacitance, and one of a worst case maximum net interconnect delay and a best case minimum net interconnect delay of a net comprising a net cell and a net interconnect in an integrated circuit design; providing a worst case margin multiplier and a best case margin multiplier for the integrated circuit design; calculating a worst case minimum net interconnect delay from the worst case maximum net interconnect delay, the coupling capacitance, the net capacitance, and the worst case margin multiplier when the worst case maximum net interconnect delay is provided; and calculating a best case maximum net interconnect delay from the best case minimum net interconnect delay, the net capacitance, and the best case margin multiplier when the best case minimum net interconnect delay is provided.