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Self-aligned split-gate flash memory cell having an integrated source-side erase structure and its contactless flash memory arrays
Self-aligned split-gate flash memory cell having an integrated source-side erase structure and its contactless flash memory arrays
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机译:具有集成的源极侧擦除结构的自对准分裂栅闪存单元及其非接触式闪存阵列
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摘要
A self-aligned split-gate flash memory cell of the present invention comprises an integrated floating-gate layer being at least formed on a first gate-dielectric layer having a first intergate-dielectric layer formed on its top and a second intergate-dielectric layer formed on its inner sidewall; a planarized control/select-gate layer being at least formed on a second gate-dielectric layer and the first second intergate-dielectric layers; a common-source and a common-drain diffusion regions; and an integrated source-side erase structure being at least formed on a portion of the common-source diffusion region and on a tunneling-dielectric layer formed over an outer sidewall of the integrated floating-gate layer. The self-aligned split-gate flash memory cells are configured into two contactless array architectures: a contactless NOR-type array and a contactless parallel common-source/drain conductive bit-lines array.
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