首页> 外国专利> Self-aligned split-gate flash memory cell having an integrated source-side erase structure and its contactless flash memory arrays

Self-aligned split-gate flash memory cell having an integrated source-side erase structure and its contactless flash memory arrays

机译:具有集成的源极侧擦除结构的自对准分裂栅闪存单元及其非接触式闪存阵列

摘要

A self-aligned split-gate flash memory cell of the present invention comprises an integrated floating-gate layer being at least formed on a first gate-dielectric layer having a first intergate-dielectric layer formed on its top and a second intergate-dielectric layer formed on its inner sidewall; a planarized control/select-gate layer being at least formed on a second gate-dielectric layer and the first second intergate-dielectric layers; a common-source and a common-drain diffusion regions; and an integrated source-side erase structure being at least formed on a portion of the common-source diffusion region and on a tunneling-dielectric layer formed over an outer sidewall of the integrated floating-gate layer. The self-aligned split-gate flash memory cells are configured into two contactless array architectures: a contactless NOR-type array and a contactless parallel common-source/drain conductive bit-lines array.
机译:本发明的自对准分裂栅闪存单元包括至少在第一栅介电层上形成的集成浮栅层,该第一栅介电层具有在其顶部形成的第一栅间介电层和第二栅间介电层。在其内侧壁上形成;至少在第二栅介电层和第一第二栅间介电层上形成平坦化的控制/选择栅层;共源极和共漏扩散区;至少在共源极扩散区的一部分上和在集成浮栅层的外侧壁上形成的隧穿电介质层上形成集成源极侧擦除结构。自对准分裂栅闪存单元被配置为两种非接触式阵列架构:非接触式NOR型阵列和非接触式并行共源极/漏极导电位线阵列。

著录项

  • 公开/公告号US6531734B1

    专利类型

  • 公开/公告日2003-03-11

    原文格式PDF

  • 申请/专利权人 SILICON BASED TECHNOLOGY CORP.;

    申请/专利号US20020153905

  • 发明设计人 CHING-YUAN WU;

    申请日2002-05-24

  • 分类号H01L297/88;

  • 国家 US

  • 入库时间 2022-08-22 00:07:02

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