Design for test to emulate a read with worse case test pattern

摘要

In the present invention a read test is performed on a selected cell. During the read test, a high impedance is connected to the bit lines of unselected memory cells which are connected to a common source line with the selected cell. The high impedance is created by a tri-state buffer that has a test mode control, and prevents leakage current from flowing from the common source line through unselected, erased cells. The inhibiting of the leakage current permits improved test margins to be applied to the reading of a selected cell.