首页> 外国专利> Clock synchronizing method and circuit varying a phase of a synchronous clock in one direction or the other according to a phase difference of the synchronous clock from a reference clock

Clock synchronizing method and circuit varying a phase of a synchronous clock in one direction or the other according to a phase difference of the synchronous clock from a reference clock

机译:时钟同步方法和电路,其根据同步时钟与参考时钟的相位差,在一个方向或另一个方向上改变同步时钟的相位

摘要

A clock synchronizing method is provided. The clock synchronizing method includes the step of detecting a phase difference of a synchronous clock from a reference clock, and the step of varying a phase of the synchronous clock in one direction when the phase difference is not within a predetermined range, and varying the phase of the synchronous clock in one of the one direction and the other direction according to the phase difference when the phase difference is within the predetermined range.
机译:提供了一种时钟同步方法。时钟同步方法包括以下步骤:从参考时钟检测同步时钟的相位差;以及当相位差不在预定范围内时,在一个方向上改变同步时钟的相位,并且改变相位的步骤。当相位差在预定范围内时,根据相位差在一个方向和另一个方向之一上同步时钟的相位差。

著录项

  • 公开/公告号US6573698B2

    专利类型

  • 公开/公告日2003-06-03

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US20010929355

  • 发明设计人 SATOSHI ETO;

    申请日2001-08-15

  • 分类号G01R231/20;

  • 国家 US

  • 入库时间 2022-08-22 00:05:19

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