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Apparatus for synchronizing phases of clocks generated by dual clock units in synchronous transmission system

机译:在同步传输系统中用于同步由双时钟单元产生的时钟相位的设备

摘要

PURPOSE: A clock phase synchronization device between dual clock units of a synchronous transmission system is provided to match effectively phases of each system clock by exchanging phase detection data of phase synchronous loops between dual clock units of a transmission system. CONSTITUTION: A master unit is formed with a digital phase detector(320), a comparison decision portion(321), a digital loop filter(322), a DAC(323), and a VCXO(324). A slave unit is formed with a digital phase detector(310), a comparison decision portion(311), a digital loop filter(312), a DAC(313), and a VCXO(314). The master unit and the slave unit receives and transmits phase detection data of the digital phase detectors(310,320) from or to each other in order to match phases of output clocks of the VCXO(314,324) of the master unit or the slave unit.
机译:目的:提供一种在同步传输系统的双时钟单元之间的时钟相位同步装置,以通过在传输系统的双时钟单元之间交换相位同步环路的相位检测数据来有效地匹配每个系统时钟的相位。组成:一个主单元由一个数字鉴相器(320),一个比较判定部分(321),一个数字环路滤波器(322),一个DAC(323)和一个VCXO(324)组成。从单元由数字相位检测器(310),比较判定部分(311),数字环路滤波器(312),DAC(313)和VCXO(314)形成。主单元和从单元彼此之间接收和发送数字相位检测器(310,320)的相位检测数据,以便匹配主单元或从单元的VCXO(314,324)的输出时钟的相位。

著录项

  • 公开/公告号KR20030000235A

    专利类型

  • 公开/公告日2003-01-06

    原文格式PDF

  • 申请/专利权人 LG ELECTRONICS INC.;

    申请/专利号KR20010035914

  • 发明设计人 KIM HYEONG SUK;

    申请日2001-06-22

  • 分类号H04L7/033;

  • 国家 KR

  • 入库时间 2022-08-21 23:48:04

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