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Method of extracting timing characteristics of transistor circuits, storage medium storing timing characteristic library, LSI designing method, and gate extraction method
Method of extracting timing characteristics of transistor circuits, storage medium storing timing characteristic library, LSI designing method, and gate extraction method
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机译:提取晶体管电路的时序特性的方法,存储时序特性库的存储介质,LSI设计方法和栅极提取方法
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摘要
A method of extracting timing characteristics from transistor circuit data of modularity design products (a module) such as a CPU core in which the extracted timing characteristics are used for the timing verification of a circuit including a module to be extracted and timing constraints when logical synthesis or timing-driven layout is made. Particularly, since conditions fit for a timing rule of the module are included in timing characteristics when timing verification is executed by simulation, verification free of pseudo error is enabled. Also, the configuration of a timing characteristic library, a storage medium storing it and an LSI designing method using the storage medium are provided.
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