首页> 外国专利> Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM

Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM

机译:非易失性半导体单晶体管单元,NOR型闪存EEPROM的逐位Vt校正操作

摘要

A method to test the erase condition of memory cells in a memory array device is achieved. The method is further extended to methods to detect and correct under erase and over erase conditions. The erase condition of a section of the memory array device is altered to form an erased section and non-erased sections. The control gates of the memory cells in the non-erased sections are forced to a normal off-state voltage sufficient to turn off erased cells. The control gates of the memory cells in non-selected subsections of the erased section are forced to a guaranteed off-state voltage that will turn off erased cells including those that are over erased. The control gates of the memory cells in a selected subsection of the erased section are forced to a check voltage. Thereafter, the bitline current of the selected subsection of the erased section is measured to determine erase condition of the selected subsection of the erase section.
机译:实现了一种测试存储阵列装置中的存储单元的擦除条件的方法。该方法进一步扩展到在擦除和过度擦除条件下检测和校正的方法。改变存储器阵列器件的一部分的擦除条件以形成擦除部分和未擦除部分。非擦除部分中的存储单元的控制栅极被强制为正常截止状态电压,该电压足以关闭已擦除单元。在擦除部分的未选择子部分中的存储单元的控制栅极被强制为保证的关态电压,该电压将关闭包括过度擦除的那些擦除单元。在擦除部分的选定子部分中的存储单元的控制栅极被强制为检查电压。此后,测量擦除部分的所选子部分的位线电流以确定擦除部分的所选子部分的擦除条件。

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