首页> 外国专利> - - 3 - Chip-Level Three-Dimensional Multi-Chip Package Having Chip Selection Pad Formed On Chip-Level And Making Method Therefor

- - 3 - Chip-Level Three-Dimensional Multi-Chip Package Having Chip Selection Pad Formed On Chip-Level And Making Method Therefor

机译:--3-具有在芯片级上形成的芯片选择垫的芯片级三维多芯片封装及其制造方法

摘要

The invention chip - provides a chip package and a method of manufacturing the same-level three-dimensional multi. Multi according to the invention automatically through the pad for N-1 of the chip select formed on level chip packages N of semiconductor integrated circuit elements are directly laminated and configuration, each integrated circuit chip select terminal formed on the devices are chip It is separated. For the chip select pads through the metal wiring and the through hole formed in the insulating layer is connected to the upper connection terminal, it is connected to the lower connection terminal via the wiring trench penetrating through the internal chip. In particular, a chip select because for the pads are connected to the upper connection terminal at the top of the pad for the chip select neighboring, each integrated circuit when the element is bonded to achieve the lamination, each of the chip select terminal are automatically separated in the stacking bottom circuit is connected to the lower connection terminals of the device.
机译:本发明的芯片-提供了一种芯片封装和一种制造相同水平的三维多面体的方法。根据本发明的多片自动通过用于形成在N-1个芯片选择的焊盘上的半导体集成电路元件的N个芯片封装被直接层压和配置,形成在器件上的每个集成电路芯片选择端子被芯片分离。对于通过金属布线的芯片选择焊盘,并且在绝缘层中形成的通孔连接到上连接端子,其经由穿过内部芯片的布线沟槽连接到下连接端子。尤其是芯片选择,因为将焊盘连接到焊盘顶部的上连接端子,以便相邻的芯片选择,每个集成电路在粘合元件以实现层压时,每个芯片选择端子都会自动堆叠底部电路中分离的端子连接到设备的下部连接端子。

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