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Memory test apparatus of semiconductor package and memory test method thereof
Memory test apparatus of semiconductor package and memory test method thereof
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机译:半导体封装的存储器测试装置及其存储器测试方法
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摘要
PURPOSE: A memory test device of a semiconductor package and a method for testing a memory of the same are provided to contact correctly a pin of a test socket with the lower lead of a stack package including two or more semiconductor packages. CONSTITUTION: A memory test device(100) is formed with a memory test portion(130), a handler portion(150), a loading portion(170), and a central control portion(110) for controlling totally the memory test device(100). The memory test portion(130), the handler portion(150), the loading portion(170), and the central control portion(110) are connected to each other by using a data bus(70) and a control bus(80). The loading portion(170) has the first and the second loading units in order to supply a semiconductor package to the memory test portion(130). The handler portion(150) loads the semiconductor package of the first loading unit on the memory test portion(130) or unloads the tested semiconductor package on the second loading unit. A tray insert is used for loading correctly the semiconductor package on the memory test portion(130).
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