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Arrangement for reducing number of fuses in semiconducting device has decompressor between fuse and fuse latch devices for reading states of fuses of activated master fuse
Arrangement for reducing number of fuses in semiconducting device has decompressor between fuse and fuse latch devices for reading states of fuses of activated master fuse
The arrangement has a fuse device with fuses associated with master fuses, a fuse latch device with fuse latches associated with master fuse latches and an evaluation stage. There is a dynamic relationship between master fuses and fuses and between master fuse and fuse latches. A decompressor enables the fuses of an activated master fuse to be read out to determine their active or inactive states and form a corresponding data string. The arrangement has a fuse device with master fuses and fuses (F), each master fuse having a given number of associated fuses, a fuse latch device with master fuse and fuse latches (FL) and an evaluation stage (S). There is a dynamic relationship between master fuses and fuses and between master fuse and fuse latches. A decompressor between the fuse device and fuse latch device enables the fuses of an activated master fuse to be read out to determine their active or inactive states and form a corresponding data string. AN Independent claim is also included for the following: a method of reducing number of fuses in semiconducting device.
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