首页> 外国专利> Method of manufacturing a vertical transistor a grid isolee a quadruple conduction channel, and circuit comprising such a transistor integrated

Method of manufacturing a vertical transistor a grid isolee a quadruple conduction channel, and circuit comprising such a transistor integrated

机译:垂直栅晶体管的制造方法,栅栅与四条导电沟道隔离,并且包括该晶体管的电路被集成

摘要

Production of a vertical transistor having an insulated gate with four-channel conduction comprises forming a vertical semiconductor column on a semiconductor substrate, and forming a dielectrically insulated semiconductor gate on the sides of the column and on the upper surface of the substrate. Formation of the column (PIL) comprises forming a first semiconductor column on the substrate, and forming a cavity in the primary column. Formation of the insulated gate comprises coating the internal walls of the cavity with a dielectric insulating material and filling the insulated cavity with gate material (14), so as to form, between the part of the insulated gate located in the cavity and the part of the insulated grid located on the sides of the column, two semiconductor connection regions (PL1, PL2) extending between the source and the drain of the transistor. An Independent claim is given for an integrated circuit comprising the vertical transistor.
机译:具有具有四通道导电的绝缘栅的垂直晶体管的制造包括在半导体衬底上形成垂直半导体柱,以及在柱的侧面和衬底的上表面上形成介电绝缘的半导体栅。柱(PIL)的形成包括在衬底上形成第一半导体柱,以及在主柱中形成腔。绝缘栅的形成包括用介电绝缘材料涂覆空腔的内壁,并用栅材料(14)填充绝缘空腔,以便在位于空腔中的绝缘栅的一部分和绝缘栅的一部分之间形成绝缘栅。绝缘栅位于柱的侧面,两个半导体连接区(PL1,PL2)在晶体管的源极和漏极之间延伸。对于包括垂直晶体管的集成电路,提出了独立权利要求。

著录项

  • 公开/公告号FR2823010B1

    专利类型

  • 公开/公告日2003-08-15

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS SA;

    申请/专利号FR20010004437

  • 发明设计人 THOMAS SKOTNICKI;EMMANUEL JOSSE;

    申请日2001-04-02

  • 分类号H01L21/336;

  • 国家 FR

  • 入库时间 2022-08-21 23:38:07

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