Semiconductor device with a Dynamic Random Access Memory type integrated memory based on the confinement of a negative or positive charge in one or other of two potential wells

摘要

An integrated memory semiconductor device comprises: (a) an integrated structure of point memory incorporating a semiconductor layer covered with an insulating envelope (CH2), between the source (S) and drain (D) regions of a transistor and interpolated between its canal region and control grid and including two potential well zones (Z1, Z3) separated by a potential barrier zone (Z2) under the control grid (GC); (b) a writing system (Vg, Vds) able to polarise the structure of point memory to confine some charge carriers selectively in one or other of the potential well zones; (c) a reading system (Vg, Vd) able to polarize the structure of point memory to detect the presence of the charge carriers in one of the potential wells. Independent claims are also included for: (a) an integrated circuit incorporating at least one of these semiconductor devices; (b) a method for the fabrication of such a semiconductor device.