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DIGITAL SYSTEM, CLOCK DELAY DETECTION CIRCUIT, AND CLOCK DELAY DETECTION METHOD

机译:数字系统,时钟延迟检测电路和时钟延迟检测方法

摘要

PROBLEM TO BE SOLVED: To provide a clock delay detection circuit and a clock delay detection method.;SOLUTION: This clock delay detection circuit is equipped with a delay detection circuit and a clock forwarding circuit. The delay detection circuit detects delays of predetermined output clock signals from input clock signals, generates an initial parameter corresponding to the delays if all the detected delays coincide with one another, continues to detect the delays until all the detected delays coincide with one another if any of the detected delays does not coincide with any of other detected delays, and generates a reset control signal in response to a system reset signal or a predetermined internal reset signal. The clock forwarding circuit executes a loading or unloading operation of input data in response to the initial parameter.;COPYRIGHT: (C)2004,JPO
机译:解决的问题:提供时钟延迟检测电路和时钟延迟检测方法。解决方案:该时钟延迟检测电路配备有延迟检测电路和时钟转发电路。延迟检测电路从输入时钟信号中检测预定输出时钟信号的延迟,如果所有检测到的延迟彼此一致,则生成与该延迟相对应的初始参数,继续检测该延迟,直到所有检测到的延迟彼此一致(如果有)。所检测到的延迟中的任意一个与任何其他所检测到的延迟都不相符,并且响应于系统复位信号或预定的内部复位信号而产生复位控制信号。时钟转发电路响应于初始参数执行输入数据的加载或卸载操作。; COPYRIGHT:(C)2004,JPO

著录项

  • 公开/公告号JP2004152288A

    专利类型

  • 公开/公告日2004-05-27

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO LTD;

    申请/专利号JP20030360359

  • 发明设计人 SHIN EIBIN;

    申请日2003-10-21

  • 分类号G06F1/12;

  • 国家 JP

  • 入库时间 2022-08-21 23:32:24

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