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Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges

机译：在自动延迟时钟边缘之间的凸起相混合时钟抖动减小电路的设计与理论分析

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Kiichi Niitsu; Osamu Kobayashi; Takahiro J. Yamaguchi; Haruo Kobayashi;
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1. Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges [J] . Kiichi Niitsu, Osamu Kobayashi, Takahiro J. Yamaguchi, IEICE Electronics Express . 2019,第13期

机译：在自动延迟时钟边缘之间的凸起相混合时钟抖动减小电路的设计与理论分析
2. Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits [J] . Kwak K., Kwon O Circuits and Systems II: Express Briefs, IEEE Transactions on . 2014,第4期

机译：使用单边沿跟踪时钟的多相时钟和数据恢复电路降低功耗的技术
3. DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT [J] . Wang Pengjun, Yu Junjun Journal of Electronics (CHINA) . 2007,第2期

机译：两阶段正弦功率时钟和时钟传输门的绝热逻辑电路设计
4. Design of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges [C] . Niitsu Kiichi, Harigai Naohiro, Hirabayashi Daiki, 2013 18th Asia and South Pacific Design Automation Conference . 2013

机译：利用自延迟时钟边沿之间的门控相位混合设计时钟抖动减少电路
5. Jitter Transfer and Jitter Tolerance Analysis of Bang-Bang Clock and Data Recovery Circuits. [D] . Gabr, Ahmed. 2011

机译：Bang-Bang时钟和数据恢复电路的抖动传递和抖动容限分析。
6. Dynamics of the Drosophila Circadian Clock: Theoretical Anti-Jitter Network and Controlled Chaos [O] . Hassan M. Fathallah-Shaykh 2010

机译：果蝇生物钟的动力学：理论抗抖动网络和受控混沌
7. Timing Jitter Analysis for Clock recovery Circuits Based on an Optoelectronic Phase-Locked Loop (OPLL) [O] . Zibar Darko, Mørk Jesper, Oxenløwe Leif Katsuo, 2005

机译：基于光电锁相环（OpLL）的时钟恢复电路定时抖动分析
8. Optimal Retiming of Multi-Phase, Level-Clocked Circuits [R] . Lockyear, B., Ebeling, C. 1991

机译：多相电平时钟电路的最佳重定时

Design and theoretical analysis of a clock jitter reduction circuit using gated phase blending between self-delayed clock edges

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