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Integrated circuit device including a layered superlattice material using the interface buffer layer

机译:包括使用界面缓冲层的层状超晶格材料的集成电路装置

摘要

An integrated circuit memory device includes a thin film layered superlattice material layer and an electrode. An interface buffer layer is formed between said thin film layered superlattice material layer and said electrode. The interface buffer layer is selected from the group consisting of: 1) simple oxides, not including bismuth, of an A-site or a B-site metal; and 2) second layered superlattice materials different from the first layered superlattice material and containing at least one A-site or B-site metal that is the same as an A-site or B-site metal in the first layered superlattice material. The oxide not including bismuth can be a complex oxide including a plurality of metals or a simple oxide including only one metal. Most preferably, the interface buffer layer is selected from the group consisting of strontium tantalate, bismuth tantalate, strontium niobium tantalate, strontium bismuth tantalate niobate, titanium oxide, and tantalum pentoxide, other simple oxides of A-site and B-site metals, and other simple oxides of one or more A-site or B-site metals.
机译:一种集成电路存储器件,包括薄膜层状超晶格材料层和电极。在所述薄膜层状超晶格材料层与所述电极之间形成界面缓冲层。界面缓冲层选自:1)A位或B位金属的简单氧化物,不包括铋。 2)不同于第一层超晶格材料的第二层超晶格材料,并且包含至少一种与第一层超晶格材料中的A位或B位金属相同的A位或B位金属。不包含铋的氧化物可以是包含多种金属的复合氧化物或仅包含一种金属的简单氧化物。最优选地,界面缓冲层选自钽酸锶,钽酸铋,铌酸锶锶,钽酸钽铋铋,氧化钛和五氧化钽,A位和B位金属的其他简单氧化物,以及一种或多种A-位或B-位金属的其他简单氧化物。

著录项

  • 公开/公告号JP2004522314A

    专利类型

  • 公开/公告日2004-07-22

    原文格式PDF

  • 申请/专利权人 松下電器産業株式会社;

    申请/专利号JP20030511300

  • 发明设计人 内山 潔;

    申请日2002-07-02

  • 分类号H01L27/105;H01L21/316;

  • 国家 JP

  • 入库时间 2022-08-21 23:27:39

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