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Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects
Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects
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机译:用于对包括晶体管栅极电容负载效应的逻辑电路模块进行建模的方法和系统
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摘要
A method and system for modeling logical circuit blocks including transistor gate capacitance loading effects provides improved simulation of logical circuit block transition times and delay times. The non-linear behavior of transistor gates of other logical circuit block inputs that are connected to the logical circuit block output is taken into account by a transition time function and a delay time function that are each separately dependent on static capacitance and transistor gate capacitance and can be used to determine logical circuit block timing and output performance. A separate N-channel and P-channel gate capacitance may also be used as inputs to the transition time and delay time functions to provide further improvement, or a ratio of N-channel to P-channel capacitances may alternatively be used as input to the transition time and delay time functions.
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