Low-power decode circuitry for a processor

摘要

A processor having improved decode logic is provided. In accordance with one embodiment, the processor includes a first decoder capable of decoding a first plurality of instructions, a second decoder capable of decoding a second plurality of instructions, and special instruction logic for implementing at least one special instruction, the at least one special instruction being an instruction that the first decoder or second decoder is not designed to directly decode for execution by an execution unit in the processor. In another embodiment, a related method is provided for decoding a processor instruction.