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TRIPLE LAYER HARD MASK FOR GATE PATTERNING TO FABRICATE SCALED CMOS TRANSISTORS
TRIPLE LAYER HARD MASK FOR GATE PATTERNING TO FABRICATE SCALED CMOS TRANSISTORS
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机译:三层硬掩模,用于选通栅极以形成标度的CMOS晶体管
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摘要
An integrated circuit employing CMOS technology employs a process integration that combines a source/drain silicide with a replacement gate process using a triple layer hardmask that is consumed during the course of processing in which a first temporary gate sidewall spacer defines an area for the formation of the raised source and drain and a second temporary spacer defines an area for the implant of the source and drain and for the siliciding of the source and drain while the temporary gate is protected from silicidaiton by the hardmask.
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