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Recess transistor (TR) gate to obtain large self-aligned contact (SAC) open margin and method of forming the same
Recess transistor (TR) gate to obtain large self-aligned contact (SAC) open margin and method of forming the same
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机译:凹陷晶体管(tr)栅极以获得大的自对准接触(sac)开裕量及其形成方法
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摘要
A memory cell of a semiconductor device and a method for forming the same, wherein the memory cell includes a substrate having active regions and field regions, a gate layer formed over the substrate, the gate layer including a plurality of access gates formed over the active regions of the substrate and a plurality of pass gates formed over the field regions of the substrate, first self-aligned contact regions formed between adjacent pass gates and access gates, and second self-aligned contact regions formed between adjacent access gates, wherein a width of each of the first self-aligned contact regions is larger than a width of each of the second self-aligned contact regions.
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