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Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits
Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits
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机译:有选择地应用分辨率增强技术来提高集成电路的性能和制造成本
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摘要
One embodiment of the present invention provides a system that applies resolution enhancement techniques (RETs) selectively to a layout of an integrated circuit. Upon receiving the layout of the integrated circuit, the system identifies a plurality of critical regions within the layout based on an analysis of one or more of, timing, dynamic power, and off-state leakage current. The system then performs a first set of aggressive RET operations on the plurality of critical regions. The system also performs a second set of less aggressive RET operations on other non-critical regions of the layout.
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