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Integrated circuits having adjacent P-type doped regions having shallow trench isolation structures without liner layers therein therebetween

机译:具有相邻的P型掺杂区的集成电路,该P型掺杂区具有浅沟槽隔离结构,其间没有衬层

摘要

An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer.
机译:集成电路衬底包括彼此间隔开的第一和第二相邻的p型掺杂区。集成电路衬底中的沟槽在第一和第二相邻的p型掺杂区之间。沟槽中的绝缘体层具有侧壁,其中该侧壁没有减小集成电路基板与绝缘体层之间的应力的层。

著录项

  • 公开/公告号US2004021197A1

    专利类型

  • 公开/公告日2004-02-05

    原文格式PDF

  • 申请/专利权人 OH YONG-CHUL;JIN GYO-YOUNG;

    申请/专利号US20030631602

  • 发明设计人 GYO-YOUNG JIN;YONG-CHUL OH;

    申请日2003-07-31

  • 分类号H01L29/00;

  • 国家 US

  • 入库时间 2022-08-21 23:16:00

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