首页> 外国专利> Integrated circuits having adjacent p-type doped regions having shallow trench isolation structures without liner layers therebetween and methods of forming same

Integrated circuits having adjacent p-type doped regions having shallow trench isolation structures without liner layers therebetween and methods of forming same

机译:具有相邻的p型掺杂区的集成电路及其形成方法,该相邻的p型掺杂区具有浅沟槽隔离结构,其间没有衬层。

摘要

An integrated circuit substrate includes first and second adjacent p-type doped regions spaced-apart from one another. A trench in the integrated circuit substrate is between the first and second adjacent p-type doped regions. An insulator layer in the trench has a side wall, wherein the side wall is free of a layer that reduces a stress between the integrated circuit substrate and the insulator layer. IMAGE
机译:集成电路基板包括彼此间隔开的第一和第二相邻的p型掺杂区。集成电路衬底中的沟槽在第一和第二相邻的p型掺杂区之间。沟槽中的绝缘体层具有侧壁,其中该侧壁没有减小集成电路基板与绝缘体层之间的应力的层。 <图像>

著录项

  • 公开/公告号EP1213757B1

    专利类型

  • 公开/公告日2007-04-11

    原文格式PDF

  • 申请/专利权人 SAMSUNG ELECTRONICS CO. LTD.;

    申请/专利号EP20010128854

  • 发明设计人 OH YONG-CHUL;JIN GYO-YOUNG;

    申请日2001-12-04

  • 分类号H01L21/762;

  • 国家 EP

  • 入库时间 2022-08-21 20:49:57

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