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Phase comparator, clock data recovery circuit and transceiver circuit
Phase comparator, clock data recovery circuit and transceiver circuit
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机译:相位比较器,时钟数据恢复电路和收发器电路
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摘要
A phase comparator comprises a latch unit for latching the input data signal in parallel on rising/falling edges of the respective clock signals respectively, an error signal output unit for outputting m error signals respectively indicative of differences in phase between the transient edge of the input data signal and the transient edges of the respective clock signals and each having a minimum pulse width of (m/2−1)×T or more, based on respective output signals produced from the latch unit and the respective clock signals, an input unit for inputting the respective output signals produced from the latch unit in parallel on the rising/falling edges of the respective clock signals and a reference signal output unit for outputting m reference signals whose pulse widths are (m/2)×T, based on output signals produced from the input unit and the respective clock signals.
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