Semiconductor integrated circuit device with embedded synchronous memory precisely operating in synchronization with high speed clock

摘要

There is provided a plurality of main control signal generating circuits each generating a plurality of main control signals, the plurality of main control signal generating circuits are sequentially activated and a prescribed main control signal generating circuit in a prescribed sequence is reset when a predetermined main control signal is activated. Local control signal is generated using rising edges of main control signals of one set and falling edges of main control signals of another set among a plurality of sets of the main control signals. Thereby, internal timing control signals changing at a high speed can be generated without suffering a restraint on a pulse width of a pulse signal due to an internal interconnection load.