Synchronous semiconductor memory device having clock synchronization circuit and circuit for controlling on/off of clock tree of the clock synchronization circuit

摘要

The present invention relates to a semiconductor circuit technology, in particular a synchronous semiconductor memory device, in more detail, to a clock tree on / off control circuit of a synchronous semiconductor memory device and a clock synchronization circuit includes a clock synchronization circuit. An object of the present invention is to provide a synchronous semiconductor memory device that can reduce current consumption in standby mode. Further, an object of the present invention is to provide a row address strobe (RAS) clock tree of clock synchronization circuit capable of controlling the clock tree, the clock synchronization circuit with only the signals related to on / off control circuit. The failure to turn off the tree, the clock output from the clock synchronization circuit in the standby mode in the prior art is due to the complexity of the control. That is, in order to define a trace on (trace on) period of the PLL clock or DLL clock had to control a data output definition signals associated with a row address strobe (RAS) and column address strobe (CAS), latency (AL, CL) and since the data output signal that define the data length changes according to (BL) of the circuit it is difficult to implement. In the present invention, the row address strobe (RAS) and then only the row address strobe (RAS) operating using associated signal after a particular clock - after securing the stability of the data output - Unconditional a circuit for turning off the tree of the clock output from the clock synchronization circuit offer.