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Integrated memory having a memory cell array with a plurality of segments and method for operating the integrated memory

机译:具有具有多个段的存储单元阵列的集成存储器以及用于操作该集成存储器的方法

摘要

An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different segments together form a common global word line. The global word line is decoded via a row decoder. The first and second local word lines are connected to a column decoder in such a way that they can be decoded individually and segment by segment in a manner dependent on a column address. The memory thus allows fast and current-saving activation of a word line.
机译:集成存储器具有存储单元阵列,该存储单元阵列被细分为多个单独的段。不同段中的第一局部字线和第二局部字线一起形成共同的全局字线。全局字线通过行解码器解码。第一和第二局部字线以这样的方式连接到列解码器,使得它们可以被独立地解码并且以取决于列地址的方式逐段地解码。存储器因此允许字线的快速且节省电流的激活。

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