Method for high speed testing with low speed semiconductor test equipment

摘要

A method for testing semiconductor memories, in accordance with the invention includes providing a tester having a plurality of data channels. The tester operates at a first clock rate. A memory device to be tested is included with a plurality of data ports connected to the data channels. The memory device has a data compression circuit for compressing test data such that a number of the plurality of data ports are available for other functions. Data is transferred between the memory device and the tester at a rate higher than the first clock rate by employing the plurality of data ports including the number of the plurality of data ports, such that the memory device operates at the higher rate and the tester operates at the first rate. In other embodiments data ports are made available by employing an on-chip addressing method. In still other embodiments, an on-chip clock receiver provides double data rate clocking of the memory device.