A method for reducing effect of a narrow channel in a transistor in a semiconductor device with a trench isolation, and such a semiconductor device.

摘要

Narrow-channel effect free DRAM cell transistor structure for submicron isolation pitch DRAMs having lowed-doped substrate and active width-independent threshold voltage by employing conductive shield in the shallow trench isolation(STI). The resulting cell transistor structure is highly immune to parasitic E-field penetration from the gate and neighbouring storage node junctions via STI and will be very appropriate for Gbit scale DRAM technology. The conductive shield is biased with the negative voltage in order to minimize the sidewall depletion in the substrate.