首页> 外国专利> METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE FOR IMPROVING LEAKAGE CURRENT CHARACTERISTIC BETWEEN ERASE GATE AND FLOATING GATE

METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE FOR IMPROVING LEAKAGE CURRENT CHARACTERISTIC BETWEEN ERASE GATE AND FLOATING GATE

机译:制造非易失性存储器以改善擦除门和浮动门之间的漏电流特性的方法

摘要

PURPOSE: A fabrication method of a non-volatile memory device is provided to improve a leakage current characteristic between an erase gate and a floating gate by forming a thin gate insulating layer of a transistor necessary for satisfying a low-voltage operating speed. CONSTITUTION: A floating gate(63a) and a control gate(65a) are formed on a cell region of a semiconductor substrate(51). An oxide layer is formed on a peripheral region of the semiconductor substrate. The oxide layer is removed therefrom and a gate insulating layer(62) is formed thereon. A conductive material layer is formed on the entire surface of the semiconductor substrate. A masking process is performed by using a photoresist. An erase gate(71a) is formed to overlap with the control gate adjacent to the cell region of the semiconductor substrate. A low-voltage transistor is formed on a peripheral region of the semiconductor substrate.
机译:用途:提供一种非易失性存储器件的制造方法,以通过形成满足低压工作速度所必需的晶体管的薄栅绝缘层来改善擦除栅和浮栅之间的泄漏电流特性。组成:浮栅(63a)和控制栅(65a)形成在半导体衬底(51)的单元区域上。氧化物层形成在半导体衬底的外围区域上。从其上去除氧化物层,并在其上形成栅极绝缘层(62)。导电材料层形成在半导体基板的整个表面上。通过使用光致抗蚀剂执行掩模工艺。形成擦除栅极(71a)以与与半导体衬底的单元区域相邻的控制栅极重叠。在半导体衬底的外围区域上形成低压晶体管。

著录项

  • 公开/公告号KR100429178B1

    专利类型

  • 公开/公告日2004-04-14

    原文格式PDF

  • 申请/专利权人 HYNIX SEMICONDUCTOR INC.;

    申请/专利号KR19970079137

  • 发明设计人 KIM JI HYEOK;

    申请日1997-12-30

  • 分类号H01L27/10;

  • 国家 KR

  • 入库时间 2022-08-21 22:47:11

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号