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Semiconductor wafer with electrically connected contact and test surfaces and after treatment process has passive contact region and test surfaces in active component region of chip
Semiconductor wafer with electrically connected contact and test surfaces and after treatment process has passive contact region and test surfaces in active component region of chip
A semiconductor wafer having many chips has electrically connected contact (1) and test (2) surfaces with the contacts being in a passive region (5) of the upper chip (1) where there are no IC components. The test surfaces are in a second, active, region (7) which comprise active components. An Independent claim is also included for an after treatment process for the wafer above.
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