Method for loading test vectors into scan chains

摘要

A circuit under test has multiple scan chains 10/11/12, 20/21/22 etc each having an input SDI connected to a common input terminal 30. Each scan chain has a separate clock signal SCK1, SCK2 etc. To load test vectors into the scan chains through common input 30, the first bits of multiple scan vectors are transmitted to inputs SDI, and the different clock times of clocks SCK1, SCK2 etc ensure that only the first bit of the appropriate test vector is loaded into the appropriate scan chain (see figure 2, not shown). The second bits of the test vectors are then transmitted and selectively clocked in the same way. The process is repeated until all the bits of the test vectors have been broadcast to the corresponding scan chains.