1st flip-flop (F0) and n other flip-flop (F1...Fn) being the false random generator which possesses the shift register which it possesses, the aforementioned each flip-flop (F0), D input, non reversal output, reversal output and the common clock (fclk) to possess input, the aforementioned 1st flip-flop (F0) to possess setting input, aforementioned each non reversal output, the NOR gate (10) through, the aforementioned 1st flip-flop (F0) to be connected by the aforementioned setting input, the aforementioned flip-flop (F0...Fn) each of the aforementioned non reversal output n is connected, the aforementioned 1st flip-flop (F0) the XOR gate (11) through in the aforementioned input, the aforementioned generator at least in the generator, one additional flip-flop (14; 18) at least one which is included additional logic gates (13, 14 and 15; It is the generator which 17, 18 and 19) it possesses, features thing. The additional logic gates the toggle do with reversal output and non reversal output, or, form additional 0 with output, or, the chop do the input signal to ideal to random, it is possible to possess the gate.
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