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randamujiyunereta

机译:随机吉语

摘要

1st flip-flop (F0) and n other flip-flop (F1...Fn) being the false random generator which possesses the shift register which it possesses, the aforementioned each flip-flop (F0), D input, non reversal output, reversal output and the common clock (fclk) to possess input, the aforementioned 1st flip-flop (F0) to possess setting input, aforementioned each non reversal output, the NOR gate (10) through, the aforementioned 1st flip-flop (F0) to be connected by the aforementioned setting input, the aforementioned flip-flop (F0...Fn) each of the aforementioned non reversal output n is connected, the aforementioned 1st flip-flop (F0) the XOR gate (11) through in the aforementioned input, the aforementioned generator at least in the generator, one additional flip-flop (14; 18) at least one which is included additional logic gates (13, 14 and 15; It is the generator which 17, 18 and 19) it possesses, features thing. The additional logic gates the toggle do with reversal output and non reversal output, or, form additional 0 with output, or, the chop do the input signal to ideal to random, it is possible to possess the gate.
机译:第一触发器(F0)和其他n个触发器(F1 ... Fn)是伪随机发生器,其具有其所拥有的移位寄存器,上述各触发器(F0),D输入,非反转输出,反向输出和公共时钟(fclk)拥有输入,上述第一触发器(F0)拥有设置输入,上述每个非反向输出,或非门(10)至上述第一触发器(F0) )通过上述设定输入连接,上述各非正向输出n的上述各触发器(F0 ... Fn)被连接,上述第1各触发器(F0)通过XOR门(11)连接。上述输入,上述发生器至少在发生器中,一个附加触发器(14; 18)至少一个,其中包括附加逻辑门(13、14和15;它是发生器17、18和19)它具有特征的东西。触发器的附加逻辑门与反向输出和非反向输出一起执行,或者与输出形成附加0,或者斩波将输入信号理想化为随机到理想状态,则可以拥有门。

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