Semiconductor integrated circuit device design apparatus, semiconductor integrated circuit design method, and semiconductor integrated circuit design program

摘要

An apparatus executes wire layout design in an integrated circuit. The apparatus includes a logic cell arrangement information acquisition unit which acquires information concerning a logic cell arrangement on a chip, a wire-grouping unit which estimates wires between logic cell terminals based on the acquired information and groups the estimated wires into each wire layer region, a via setting unit which sets via wire for pulling a logic cell terminal up to a wire layer region, a wire information extraction unit which extracts wire information for each of the wire groups and a routing execution unit which executes routing between the logic cell terminals for each of the wire layer regions based on the extracted information. A method for executing wire layout design in an integrated circuit includes acquiring information concerning a logic cell arrangement on a chip, executing wire-grouping, setting via wire for pulling a logic cell terminal up to a wire layer region, extracting wire information for each of the wire groups, and executing routing between the logic cell terminals for each of the wire layer regions based on the extracted information. The wire-grouping contains estimating wires between logic cell terminals based on the acquired information concerning the logic cell arrangement and dividing the estimated wires into each group of a wire layer region.